IPC J-STD-003 Revision C
Original price was: $168.00.$101.00Current price is: $101.00.
Solderability Tests for Printed Boards
standard by Association Connecting Electronics Industries, 09/01/2013
J-STD-003C prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands and plated-through holes utilizing either tin-lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability. Revision “C” contains the latest information about gauge repeatability and reproducibility (GR&R) of solderability tests as well as updated illustrations.
Product Details
- Published:
- 09/01/2013
- Number of Pages:
- 44
- File Size:
- 1 file , 1.7 MB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus
